The present invention relates to a semiconductor design technology, and more particularly, to a semiconductor device for generating a synchronization clock signal and outputting a plurality of data in synchronization with the synchronization clock signal, and a driving method thereof.
In general, a semiconductor memory device such as Double Data Rate Synchronous DRAM (DDR SDRAM) includes tens of millions of memory cells for storing data. Such a semiconductor memory device stores or outputs data according to a command from a central processing unit (CPU). For example, when a CPU requires a write operation, a semiconductor memory device stores data in a memory cell corresponding to an address inputted from the CPU. When a CPU requests to perform a read operation, a semiconductor memory device outputs data stored in a memory cell corresponding to an address inputted from the CPU. At this point, data inputted through a pad in a write operation is inputted to a memory cell through a data input path, and data stored in a memory cell is outputted through a pad after passing through a data output path for a read operation.
Lately, semiconductor memory devices are being manufactured for high integration, high speed operation, and large capacity. Accordingly, the number of pads has increased. A plurality of data outputted through a plurality of pads are transferred to other devices. Here, the semiconductor memory devices output a plurality of data by synchronizing the plurality of data with one synchronization clock signal generally. Therefore, a semiconductor memory device includes a circuit for synchronizing a plurality of data with a synchronization clock signal. Not only the semiconductor memory device but also a general semiconductor device includes a circuit for performing such a synchronization operation in order to process a plurality of data.
FIG. 1 is a block diagram illustrating a partial structure of a conventional semiconductor device.
Referring to FIG. 1, a typical semiconductor device includes a clock driver 110, a plurality of synchronizers 130, a plurality of data drivers 150, and a plurality of pads 170. For illustration purposes, FIG. 1 shows the typical semiconductor device which includes 16 pads 170, that is, 0th to 15th PAD as an example. Accordingly, the typical semiconductor device includes 16 data drivers 150 such as 0th to 15th DATA DRIVER and 16 synchronizers 130 such as 0th to 15th SYNCHRONIZER corresponding to the 16 pads.
The clock driver 110 generates a synchronization clock signal CLK_SYC by buffering an internal clock signal CLK_INN. Generally a frequency of an internal clock signal CLK_INN and a frequency of a synchronization clock signal CLK_SYC are identical to each other.
The 0th to 15th synchronizers 130 receive the 0th to 15th data DAT<0:15>, synchronize the received data with the synchronization clock signal CLK_SYC, and output the synchronized data, respectively. The 0th to 15th data drivers 151 drive the synchronized data outputted from the 0th to 15th synchronizers 130 and output the driven data to the 0th to 15th pads 170. 0th to 15th output data DQ<0:15> outputted through the 0th to 15th pads 170 are transferred to devices that requires that. As described above, the 0th to 15th output data DQ<0:15> are generally synchronized with the synchronization clock signal CLK_SYC and outputted.
Hereinafter, problems of a typical semiconductor device having a structure shown in FIG. 1 will be described.
The synchronization clock signal CLK_SYC outputted from the clock driver 110 is applied to the 0th to 15th synchronizers 130 through a comparatively long clock transmission path LN. Therefore, the synchronization clock signal CLK_SYC is applied to each of the 0th to 15th synchronizers 130 at different time points. That is, if the synchronization clock signal CLK_SYC is applied to the 0th synchronizer 130_0 at a time point Δt0, a time point of applying the synchronization clock signal CLK_SYC to the first synchronizer 130_1 becomes a time delayed by as much as Δt1 from Δt0, and a time of applying a synchronization clock signal CLK_SYC to the second synchronizer 130_2 becomes a time delayed by as much as Δt2 from Δt0. Therefore, a time point of applying the synchronization clock signal CLK_SYC to the 15th synchronizer 130_15 becomes a time delayed by as much as Δt15 from Δt0. After all, a skew is reflected at the synchronization clock signal applied at different time points in view of 0th to 15th synchronizers 130.
FIG. 2 illustrates 0th to 15th output data DQ<0:15> outputted from 0th to 15th pads 170 of FIG. 1.
As shown in FIG. 2, the skew of the synchronization clock signal CLK_SYC is reflected at the 0th to 15th output data DQ<0:15>. That is, the 0th to 15th output data DQ<0:15> are outputted at the different time points corresponding to Δt0 to Δt15. Therefore, a valid data range of the 0th to 15th output data DQ<0:15> becomes very small compared to a real data range. The small valid data range means difficulty in recognizing 0th to 15th data DQ<0:15> in a device receiving the 0th to 15th output data DQ<0:15>. In order to resolve this problem, a semiconductor device of FIG. 3 was introduced.
FIG. 3 is a block diagram illustrating another conventional semiconductor device.
Compared to the semiconductor device of FIG. 1, a clock transmission path for transferring a synchronization clock signal CLK_SYC is hierarchically layered into a first clock transmission path LN1, a second clock transmission line LN2, and a third clock transmission paths LN3_1 and LN3_2. In other words, by grouping the synchronizers 310, clock transmission paths corresponding to each group are designed to have same length. For example, 0th to 3rd synchronizers 310 are classified as a first group, 12th to 15th synchronizers 330 are classified as a fourth group, and, not shown, 4th to 7th and 8th to 11th synchronizers are classified as a second and a third groups, respectively.
Therefore, the synchronization clock signal CLK_SYC is outputted as first to fourth synchronization clock signals CLK_SYC1, CLK_SYC2, CLK_SYC3, and CLK_SYC4 at the same operation time through the first, second, and third clock transmission paths LN1, LN2, and LN3_1 and LN3_2. The outputted first to fourth synchronization clock signals CLK_SYC1, CLK_SYC2, CLK_SYC3, and CLK_SYC4 are applied to each synchronizers in the first to fourth groups through fourth clock transmission paths LN4_1 and LN4_4. The first to fourth synchronization clock signals CLK_SYC1, CLK_SYC2, CLK_SYC3, and CLK_SYC4 are used to synchronize a plurality of data. Since subsequent operations are identical to the operation of the semiconductor device shown in FIG. 1, detail description thereof is omitted.
However, the semiconductor device of FIG. 3 has following problems. For illustration purposes, only the first and fourth groups will be representatively described.
The time of applying the first synchronization clock signal CLK_SYC1 to the first group and that of applying the fourth synchronization clock signal CLK_SYC4 to the fourth group are the same because the first, second, and third clock transmission paths LN1, LN2, LN3_1, and LN3_2 are identically arranged. However, the first clock signal CLK_SYC1 passes through the fourth clock transmission path LN4_1 corresponding to the first group while the first clock signal CLK_SYC1 is applied to the 0th to 3rd synchronizers of the first group. That is, the 0th to 3rd synchronizers of the first group receive the first synchronization clock signal CLK_SYC which Δt0, Δt1, Δt2, and Δt3 are respectively associated with. After all, the first synchronization clock signal CLK_SYC1, which is applied to the 0th to 3rd synchronizers at different time points, has an associated skew from the perspective of the 0th to 3rd synchronizers. The fourth synchronization clock signal CLK_SYC4, which is applied through the fourth clock transmission path LN4_4 corresponding to the fourth group, has a skew. Although not shown in the drawings, such a skew is reflected at each synchronizer in the second and third groups.
The skews of first to fourth synchronization clock signals CLK_SYC1, CLK_SYC2, CLK_SYC3, and CLK_SYC4 are reflected at the output signal of each synchronizer and influence the 0th to 15th output data DQ<0:15> through the 0th to 15th pads.
FIG. 4 illustrates 0th to 15th output data DQ<0:15> outputted from 0th to 15th pads of FIG. 3.
As shown in FIG. 4, the skew of the first to fourth synchronization clock signals CLK_SYC1, CLK_SYC2, CLK_SYC3, and CLK_SYC4 is reflected at the 0th to 15th output data DQ<0:15>. That is, the 0th to 15th output data DQ<0:15> are outputted at different time points corresponding to Δt0 to Δt3. Therefore, although the valid data range of the 0th to 15th output data DQ<0:15> may be obtained larger than it is in FIG. 2, but becomes smaller than a real data range.
Referring back to FIG. 3, the semiconductor device has the layered clock transmission paths for transmitting the synchronization clock signal CLK_SYC. It is preferred to dispose each of the layered clock transmission paths with the same structure. Accordingly, it is possible to stably secure a valid data range. If the layered clock transmission path is extended further, the valid data range can be extended further as well. That is, if the layering of the clock transmission path is extended to be directly corresponding to the 0th to 15th synchronizers, the valid data range can be extended further. However, such extension of the clock transmission path may become a limitation in designing a layout due to the high integration of the semiconductor device. The embodiments of the present invention relates to a semiconductor device that can secure sufficient valid data range without layering a clock transmission path.